(1) Field of the Invention
This invention relates to a packaging substrate and a method of forming the same, and more particularly to a packaging substrate without a plating bar.
(2) Description of Related Art
As semiconductor fabrication technology has been effectively improving, it is the trend to have a central processing unit (CPU) characterized with small-size, multi-function, and high-speed. Such a CPU needs an increased number of input/output (I/O) contacts to transmit data for various purposes, and is usually formed with arrayed I/O pads to increase I/O density (pitch≦200 μm). To deal with the arrayed I/O pads, a flip-chip packaging method, in which a die is connected to a packaging substrate by using bumps, becomes more popular.
FIGS. 1A to 1D depict schematic cross-section views of a fabrication method of a packaging substrate for flip-chip packaging. Firstly, as shown in FIG. 1A, a substrate 100 is provided with through holes 110 formed by mechanical or laser drilling. Afterward, the through holes 110 are plated with conductive material, and then conductive layers 102 connecting to the plated through holes 110 are formed on opposing surfaces of the substrate 100. Then, as shown in FIG. 1B, a lithographic and etching process is carried out toward the conductive layers 102 to form a first conductive pattern 120 on an upper surface of the substrate 100 and a second conductive pattern 130 on a bottom surface of the substrate 100. Through the plated through holes 110, the first conductive pattern 120 can electrically connect with the second conductive pattern 130. It should be noted that a plating bar 140 electrically connecting to the first conductive pattern 120 and the second conductive pattern 130 must be simultaneously formed in the step shown in FIG. 1B.
Afterward, as shown in FIG. 1C, a first solder mask (SM) 122 and a second solder mask 132 are formed on the opposing surfaces of the substrate 100 for covering predetermined portions of the two conductive patterns 120 and 130 respectively to define particular connecting positions. Then, as shown in FIG. 1D, a plurality of metal pads 124 and 134 are formed in the openings of the solder masks 122 and 132 by plating. It is noted that the plating bar 140 is utilized for providing negative charges to both the conductive patterns 120 and 130. Thus, the conductive patterns 120 and 130 become cathodes in the plating process shown in FIG. 1D, which can let metal ions adhered thereon.
However, the existence of the plating bar 140 may sacrifice a significant amount of area size on the substrate 100 for laying the conductive patterns 120 and 130, and the number of connecting positions on the substrate 100 is thus limited.
On the other hand, an electroless plating technology, which no plating bar 140 is needed, can be used for forming a highly smooth plating surface. However, the electroless plating technology has a primary drawback that poor adhesion is resulted between the plating layer and the plated layer. The metal pads 124 and 134 formed in the process of FIG. 1D need a tightly adhesion toward the conductive patterns 120 and 130 so as to guarantee a reliable signal transmission path. Therefore, the electroless plating technology is not suitable in the present situation.
Moreover, in the plating process of FIG. 1D, the metal pads 124 and 134 are respectively formed simultaneously on the first conductive pattern 120 and the second conductive pattern 130 so that identical material composition and similar thickness can be achieved. However, metal pads 124 and 134 arranged with different pitches on the opposing surfaces of the substrate 100 are preferred in most packaging designs for adapting different connecting means, such as pins and bumps, on the opposing surfaces. For example, in a typical flip-chip packaging, the metal pads 124 on the upper surface of the substrate 100 are used to connect to a die with high density arrayed pads through the bumps, and the metal pads 134 on the bottom surface are used to connect to a main board by using pins, bumps, or other conducting means. The pitch of the metal pads 124 on the upper surface is thus smaller than that of the metal pads 134 on the bottom surface.
For the electroless plating technology is not suitable for plating metal pads 124 and 134 onto the conductive patterns 120 and 130, an additional plating bar 140 is thus required for providing negative charges to the conductive patterns 120 and 130. In addition, the plated metal pads with identical material composition and similar thickness may limit the adaptability of such packaging substrate.